What Affect Chip Warpage?


Release time:

2019-03-15

In the manufacturing process of camera modules, the most commonly used method to pack sensor chips or imager is COB (Chip on Board). It means the sensor chips are directly bonded to PCB (printed circuit board) or FPC (flexible printed circuit) using a thermally cured die attach adhesive (DA). After curing the DA at about 70oC to 100oC and cooling down to room temperature, imagers may show chip warpage which can cause undesired image distortions.

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Warpage is a common phenomenon in semiconductor packaging. Just like imager packaging, warpage is caused by thermal mismatch between the chip and the substrate, as the thermal expansion coefficient (CTE) of Si Chip being significantly smaller than that of the substrate. At curing temperature, the Si Chip and the copper substrate are flat and parallel to each other.  During cooling, the substrate shrinks more than the chip. With the cured adhesive hindering horizontal shifts, chip warpage becomes the only solution to release thermal stresses.

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There are many factors affecting the magnitude of chip warpage. The bigger and thinner the chip is, the higher the warpage. Substrate also affects chip warpage. One of the clever ideas to reduce warpage is to use a multi-layer PCB. Asymmetric substrates may show smiling faces at elevated temperatures. So when cooling down to room temperature, the chips may show negligible warpage or even a bit of a smiling face.

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Warpage can also be affected by die attach adhesives. Factors to consider include adhesive cure shrinkage, CTE, Tg and modulus. Over the last 14 years, Yongoo has studied warpage on numerous chip and substrate combinations. By bringing its accumulated knowledge to camera module assembly, Yongoo has successfully developed Y-Bond S751 series of imager die attach adhesives. These products not only can deliver chip warpage to meet customers designs, but also have significantly better heat and humidity resistance.  

 

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